1. Field of the Invention
The present invention relates generally to the field of semiconductor memories, particularly to non-volatile memories and even more particularly to electrically programmable non-volatile memories. More specifically, the invention concerns dual charge storage location non-volatile semiconductor memory cells.
2. Description of the Related Art
As known, the information storage mechanism in non-volatile memory cells such as EPROMs, EEPROMs and Flash EEPROMs is based on the possibility of having an electric charge trapped in a charge storage element. The presence of an electric charge in the charge storage element determines a change in the memory cell threshold voltage. Such a threshold voltage change can be assessed by measuring a current sunk by the memory cell in a prescribed bias condition.
Typically, the charge storage element is represented by a polysilicon floating gate insulatively placed over the memory cell channel region and capacitively coupled to a polysilicon control gate. Charge carriers can be injected into the floating gate by means of the hot electron injection mechanism, as in EPROMs and Flash EPROMs, or by tunneling, as in EEPROMs. The presence of an electric charge in the floating gate affects the formation of a conductive channel in the channel region.
Up to some years ago; each memory cell was used to store one bit of information, corresponding to the absence (a condition conventionally interpreted as a logic “1”) or the presence (logic “0”) in the floating gate of an electric charge equal to or greater than a prescribed minimum amount.
The constant trend towards the increase of semiconductor memory storage capacity per unit chip area has however suggested that each memory cell could be used to store more than one bit.
Memory cells have therefore been proposed whose threshold voltage can take one of a plurality of threshold voltage levels. In such memory cells, commonly referred to as multi-level memory cells, the amount of charge trapped in the floating gate is precisely controlled and can take more than two values, for example four. To each value of electric charge there corresponds a respective threshold voltage of the memory cell. For example, a multi-level memory cell having four admissible threshold voltages is able to store two bits.
More recently, memory cells having two charge storage locations have been proposed. In these memory cells it is possible to have an electric charge trapped in two physically distinct locations of the memory cell, normally at each side of the channel region thereof, near the memory cell source/drain regions. These memory cells are therefore intrinsically adapted to store two bits.
Two types of dual charge storage location memory cells are known in the art.
A first type of dual charge storage location memory cell is described for example in U.S. Pat. No. 5,949,711, which is incorporated herein by reference in its entirety. The memory cell comprises a polysilicon control gate insulatively placed over a channel region. At both sides of the control gate, near the source/drain diffusions, two electrically isolated spacer-like elements of polysilicon form two floating gates.
Charge can be selectively injected into each floating gate and be trapped therein. Each floating gate controls a short portion of the memory cell channel.
Each one of the source/drain diffusions acts as a source electrode when reading the value of the charge trapped in the adjacent floating gate, and as a drain electrode when reading the value of the charge trapped in the opposite floating gate.
As the traditional single bit or multi-level memory cells having a single floating gate, this dual charge storage location memory cell relies for its operation on the capacitive coupling between the control gate and the two floating gates.
However, due to the physical location of the two floating gates at the sides of the control gate, the areas of coupling between the latter and the former are rather small. The capacitive coupling between the control gate and the floating gate is therefore scarce, thus allowing a small amount of charge to be injected. Additionally, from a practical viewpoint it is difficult to form the two spacer-like polysilicon floating gates at the sides of the control gate.
A second type of dual charge storage location memory cells is described for example in U.S. Pat. No. 6,011,725, which is incorporated herein by reference in its entirety. In this case the memory cell comprises a polysilicon conductive gate insulatively placed over a channel region with interposition of an oxide-nitride-oxide (ONO) stack or sandwich of layers, in which the nitride layer acts as a charge-trapping layer. Charge can be injected into and trapped in two separated and separately chargeable areas found within the nitride layer, near the memory cell source/drain regions. The latter, as in the first type of dual charge storage location memory cell described above, change their role of source/drain electrodes while reading the charge trapped in one or the other of the two areas.
Compared to the first type previously described, this dual charge storage location memory cell requires one less polysilicon layer, which simplifies the manufacturing process thereof and ensures a better reproducibility, thanks to the fact that the memory cell is highly planar. However, this structure is affected by a number of other problems, some of which will now be discussed.
In principle, the charge injected into the nitride layer should remain localized at the two sides thereof, near the charge injection regions, i.e., near the source/drain regions. The localization of the injected charge is indispensable for the memory cell to be capable of storing two bits. However, for several reasons the distribution of the charges injected into the nitride layer departs from the ideal one.
For example, during the memory cell-programming phase, the electric field, which initially (i.e., when no charges have yet been injected into the nitride layer) is favorable to the injection of charges at the sides of the nitride layer, progressively changes due to the very presence in the nitride layer of already injected charges, which have a screening effect. Consequently, the electric field progressively favors the injection and trapping of charges at the center of the nitride layer. The charges injected into one of the two chargeable areas of the nitride layer to program one of the two bits of the memory cell may even propagate to reach the opposite chargeable area, thus inducing a spurious programming of the other bit.
Additionally, during the programming phase a secondary mechanism known as CHISEL causes charges to be injected into the central portion of the nitride layer. This contributes to decreasing the localization of the injected charges. The CHISEL mechanism is enhanced by the unavoidable presence, in series to the source/drain regions of the memory cells, of parasitic resistances, which alter the memory cells effective biasing conditions. It is to be observed that normally the CHISEL mechanism is purposely exploited to limit the current consumption in programming, an important feature for memory devices which have to support a high degree of parallelism in programming, such as the memory devices for mass storage memory cards, and a real must in all those memory devices designed to operate with a Single Power Supply (“SPS”). Thus, in order to try and keep the injected charge localized, the otherwise beneficial CHISEL effect should be somehow inhibited, with a negative impact on the current consumption in programming. As a consequence, the degree of parallelism in programming has to be necessarily strongly limited, especially in SPS memory devices.
Also, phenomena of local saturation and charge redistribution effects within the nitride layer tend to reduce the localization of the charges injected into one of the two chargeable areas of the nitride layer, with a consequent spread of charges towards the central portion of the nitride layer and even towards the opposite chargeable area.
As a consequence the charges injected into one of the two chargeable areas, instead of being localized at that chargeable area, progressively tend to be delocalized in the central portion of the nitride layer, over the central portion of the memory cell channel region, and in the opposite chargeable area.
In general, these charges affect the operation of the memory cell, by modifying the threshold voltage thereof in an uncontrolled manner. The redistribution of the charges injected into one side of the nitride layer towards the central portion and towards the opposite side thereof may also cause a loss of the stored information.
The repetition of write/erase cycles exacerbates these charge redistribution effects. The distributions of threshold voltages corresponding to a programmed and to an erased bit tend therefore to spread. As a consequence, the threshold voltage shift, which the memory cell has to undergo for programming one bit, must be relatively high. This has the negative consequence of accelerating the memory cell aging, because the effects of redistribution of the injected charges are more pronounced the higher the amount of injected electric charges. The more charges are injected into one side of the nitride layer, the more charges tend to be located at the central portion and at the opposite side of the nitride layer, the more difficult is to remove the charges during the erase operation, the wider the distributions of threshold voltages. Another drawback of submitting the memory cell to a high threshold voltage shift is the need of applying to the memory cell drain region a relatively high potential for a relatively long period of time: this has a soft erase effect on the memory cells belonging to the same column of the memory cell array as the memory cell under programming.
Additionally, the poor control of the amount of charges trapped in the useful positions of the nitride layer, together with the need of having a high threshold voltage shift for making a programmed bit distinguishable from an erased one, prevents from trying to increase the storage capacity by adopting a multi-level approach. Even worse, due to their position, the charges located in the central portion of the nitride layer are hardly removed during the memory cell-erasing phase. This means that the amount of charges trapped in the central portion of the nitride layer tends to rapidly increase with the number of program/erase cycles to which the memory cell is submitted. This causes a rapid increase of the time needed to erase the memory cell, up to a condition such that the memory cell cannot be erased any more.
It is to be observed that the above problems become more serious the smaller the memory cell dimensions, and therefore pose a limitation to the memory cell shrinkage.
In U.S. Pat. No. 6,248,633 B1, which is incorporated herein by reference in its entirety, a dual bit memory cell with a twin MONOS structure is disclosed. The memory cell comprises two polysilicon sidewall control gates placed over a composite ONO stack at both sides of a polysilicon word gate. The latter is placed over a gate oxide layer.
The nitride layer within the ONO stack that is under each sidewall control gate is the region for electron memory storage. Since the two nitride layer regions under the two sidewall control gates are physically separated from each other, this structure appears not to be affected by the problem of charge confinement previously discussed.
However, the various processes for manufacturing the MONOS dual charge storage location memory cell described in this document appear rather complicated. For example, use is made of disposable polysilicon sidewall spacers to fabricate the memory cell channel, which increases the process steps.